1. Field of the Invention
The invention relates to integrated circuit memories and more particularly to non-volatile memories, which use a floating gate transistor as the elementary information storage cell.
2. Description of the Prior Art
In such memories, a floating gate covers a field effect transistor channel, and a control gate covers the floating gate. The floating gate is insulated from the control gate and from the channel by thin insulating layers. The electrical programming and erasing of the memory consist of an injection and an extraction of electrons from the floating gate across the insulating layer. As a function of the quantity of charges trapped in the floating gate, the minimum reading voltage which it is necessary to apply to the control gate to make the transistor conductive (or conversely to block it) is of varying size. With a fixed reading voltage applied to the floating gate, it is consequently possible to determine what is the state (programmed or unprogrammed) of the transistor. This state represents the binary information stored in the transistor.
In order to form memories able to store a certain information quantity, the cells are arranged in matrix networks or arrays, the cells being arranged in column and row form. All the cells of a single physical row of the array are connected to the same conductor (generally known as a word line) and all the cells of the same column are connected to the same column conductor (generally called the bit line). The word line is used for designating the cells of a given row. The bit line is used for reading or writing information in the cell, which is located at the junction of the bit line and the designated word line.
In order that the cells can be organized as a matrix network, there must be a possibility of performing an operation on a given cell without affecting the non-designated cells. This means that it must be possible to apply given potentials to a single cell, across the bit line and the word line which intersect at the location of said cell, without the potentials applied to the other cells of the same word line or the same bit line affecting said other cells. If this were not the case, it would not be possible to have individual access to the informations contained in the different cells.
In the existing industrial procedure, use is made of two major principles for producing electrically programmable and erasable floating gate memories, which can be organized in matrix network form and which can be individually selected within said network.
The first principle is that of electrically programmable and erasable memories or EEPROM. These memories are programmed and erased by the application of an electric field across a very thin oxide separating the floating gate from the channel. The electric charges pass through the insulating layer by the Fowler-Nordheim tunnelling effect. The transistor is not conductive during programming or erasing. The charge passage direction (erasing or programming) is defined by the direction of the field applied. The field is applied by raising the control gate to a high potential (approximately 20 volts) and the drain to earth or grounded, or vice versa. The source is at earth for the injection of electrons into the floating gate and is under high impedance for electron extraction.
If this transistor was used as the memory cell, it would not be possible to organize a matrix network of individually programmable and erasable cells, because it would not be possible to apply the programming or erasing voltages to the drain or the floating gate across a bit line or a word line connected to other cells without programming or erasing said other cells at the same time.
This is the reason why, for conventional EEPROM memories, the cell is constituted by the series arrangement of a floating gate transistor and a selection transistor. The gate of the selection transistor is controlled by the word line and not by the floating gate transistor. Under these conditions it becomes possible to select the reading or writing of a floating gate transistor by deselecting the other cells. Making the selection transistor conductive authorizes the application of a given drain voltage to the transistors of an entire line, but a high control gate or drain voltage is only applied to the desired column.
The other category of memory cells, which is used industrially and which can be organized into a matrix network is the EPROM. The floating gate transistor is used alone and there is no selection transistor. However, programming takes place by the so-called "hot carrier" effect, i.e. it is not sufficient to apply a high electric field of the channel to the floating gate to enable the electrons to pass and instead said electrons must be accelerated beforehand in the conductive channel in order to acquire an adequate energy. Therefore programming takes place by applying a high voltage simultaneously to the drain and the control gate, the source being grounded or earthed. The transistors of the other lines, which do not have a high voltage on their gate, and the transistors of the other columns, which do not have a high voltage on their drain, are not programmed and are also not erased.
For erasing purposes, in the case of so-called flash EPROM memories, high positive voltage pulses are applied to the drain or source, whilst keeping the control gate earthed. However, there is a total erasure and individual access to the different cells is not possible. If absolutely necessary, the memory could be subdivided into separately erasable sectors.
Both EPROMS and EEPROMS suffer from disadvantages, which it would be desirable to eliminate or at least reduce.
EPROMS consume a large amount of current on programming, due to the need of making the transistors conductive under high voltages. It is necessary to have both a high voltage (7 to 15 V) and a high current (approximately 1 milliampere per cell). The high voltage can be supplied from the outside, but this requires the memory user to provide said supply, in addition to the standard low voltage supply necessary for operation outside the programming phase. Alternatively the high voltage is produced by a charge pump within the integrated circuit. However, it is difficult to produce a charge pump producing both a high voltage and a high current. Moreover, it is only possible to program a small number of cells at once, if destructive currents are to be avoided. This can cause a significant problem during the testing of memories, because the manufacturer cannot devote an excessive testing period to each circuit. Finally, EPROMS suffer from the disadvantage of requiring a programming cycle in two stages. Thus, it is not possible to program an information word without having previously completely erased the memory, because it is not possible to erase an individual cell.
EEPROMS suffer from none of these disadvantages. However, they have larger overall dimensions due to the selection transistor necessarily associated therewith when arranged in matrix network form.
An object of the invention is to propose a novel memory cell, which to the greatest possible extent obviates the disadvantages of the prior art cells.